1. Field of the Invention
The present invention relates to a method for fabricating an inductor structure or a dual damascene structure, and more particularly, to a method for fabricating an inductor structure or a dual damascene structure by means of a polymer-removing step.
2. Description of the Prior Art
Inductors built in semiconductor wafers are widely used in CMOS based radio frequency circuits, such as low-noise amplifiers, voltage-controlled oscillators, and power amplifiers. Generally speaking, the inductor is usually a spiral conductor in top view of the semiconductor wafer, where the conductor fills a spiral trench formed in a dielectric layer of the semiconductor wafer.
Please refer to FIGS. 1-6. FIGS. 1-6 are schematic cross-sectional diagrams illustrating a method for forming an inductor structure in a semiconductor wafer 10 according to the prior art. Since an inductor is usually a spiral conductor in top view of the semiconductor wafer, it is to be understood by a person skilled in this art that FIGS. 1-6 only show parts of the inductor structure, and the other parts of the inductor structure can be formed simultaneously. As shown in FIG. 1, a semiconductor wafer 10 is provided first. The semiconductor wafer 10 includes a substrate 12, a barrier layer 14 covering the substrate 12, a dielectric layer 16 located on the barrier layer 14, and a patterned barrier layer 18 positioned on the dielectric layer 16.
The substrate 12 includes three dielectric layers 22, 24, 26 positioned from bottom to top, a barrier layer 32 located between the dielectric layer 22 and the dielectric layer 24, a barrier layer 34 located between the dielectric layer 24 and the dielectric layer 26, an interconnect structure 36 positioned in the dielectric layer 22, and an interconnect structure 38 positioned in the dielectric layers 24 and 26. The interconnect structures 36 and 38 are formed for electrically connecting to the follow-up inductor structure and other components in the semiconductor wafer 10. The barrier layers 14, 18, 32, 34 can include silicon oxynitride (SiON) layers or silicon nitride (SiN) layers. The patterned barrier layer 18 is formed by means of a lithographic and etching process for defining a via hole pattern of the inductor structure. As known by those skilled in this art, parts of the dielectric layer 16 located under the opening of the patterned barrier layer 18 may be etched by the above-mentioned lithographic and etching process.
After that, as shown in FIG. 2, a deposition process is performed to form a dielectric layer 42 on the surface of the semiconductor wafer 10. The opening of the patterned barrier layer 18 and the recess of the dielectric layer 16 are filled with the dielectric layer 42. A patterned mask 44 is thereafter formed on the dielectric layer 42 to define an inductor trench pattern of the inductor structure.
As shown in FIG. 3, an etching process is performed to remove a portion of the dielectric layer 42 through the opening of the patterned mask 44 until the surface of the barrier layer 14 is exposed so as to form an inductor pattern opening 54 of the inductor structure. In this etching process, the barrier layer 14 functions as an etching stop layer. The inductor pattern opening 54 of the inductor structure includes an inductor trench 56 and two via holes 58. The inductor trench 56 has a spiral shape in top view of the semiconductor wafer 10, and the via holes 58 connect the inductor trench 56 with the interconnect structures 36, 38 below. It should be noted that FIGS. 1-6 only show parts of the inductor trench 56, and one of the via holes 58. As mentioned above, the other parts of the inductor structure can be formed simultaneously.
However, the thicker inductor film thickness is required for the quality factor (Q) improvement such that the higher selectivity of the etching gases are needed to achieve. Thus, the residues, such as polymers 52, are easily formed on the sidewall and on the bottom of the inductor trench 56 and of the via holes 58 during the etching process, where the polymers 52 usually comprise high-molecule polymers with carbon, silicon, nitrogen, fluorine, titanium, or other impurities. The polymers 52 covering the sidewall of the inductor trench 56 and the via holes 58 influence the pattern define and the quality of inductor structure.
As shown in FIG. 4, a cleaning process is next carried out to remove the polymers 52. In order to remove the polymers 52, a liquid solvent having high cost has to be used in the prior art method. After the polymers 52 are removed by the high-cost liquid solvent, an etching process is performed to etch the barrier layer 14 so as to expose the interconnect structure 38
As shown in FIG. 5, a barrier layer 62 can be deposited on the surface of the inductor pattern opening 54 for preventing the copper migration from the interconnect layer to the other parts of the semiconductor wafer 10. The barrier layer 62 can be made from tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti) or metal materials with high melting points. Afterward, a physical vapor deposition (PVD) process is performed to form a thin seed layer (not shown in the figures) on the surface of the barrier layer 62.
Subsequently, as shown in FIG. 6, a copper layer is thereafter formed to fill the inductor pattern opening 54. The filling copper layer in the inductor pattern opening 54 becomes an inductor structure 64, and the inductor structure 64 is electrically connected to the interconnect structure 38 below.
Polymers 52 are easily formed on the inductor pattern opening 54 during the etching process of forming the inductor pattern opening 54. However, when the etching process of forming the inductor pattern opening 54 is performed, the polymers 52 are obstructions and retardations that elongate the process. Especially, in order to promote the quality factors (Q) of inductors, inductor trenches having high aspect ratios are applied to the manufacturing process of inductors, and the etching time will be extremely elongated by these polymers 52.
On the other hand, since the polymers 52 are hardly etched by the etching process of forming the inductor pattern opening 54, the exposed area of the inductor pattern opening 54 is rough and uneven. The inductor pattern opening 54 may even be deformed due to the terminal effect caused by the polymers 52. Accordingly, the following-formed inductor structure 64 has unfavorable structure, and the quality factors of the inductor structure 64 decreases.
In addition, the above-mentioned polymers have to be cleaned through using high-cost solvent and elongated etching time. Since the costs of solvent or chemical materials and the amounts of the wafer through are generally the key contributors of the semiconductor process cost, how to improve the method of fabricating the inductor structure 64 to reduce process cost is still an important issue.